1. Field of the Invention
The present invention relates generally to a fully differential type amplifier circuit using a differential difference amplifier (DDA).
2. Description of the Related Background Art
Conventionally, in order to form a non-inverting amplifier having large input impedance, a technique based on a fully differential type (balanced type) DDA is employed. The balanced type DDA is shown in a symbolic diagram of FIG. 1 and in a circuit diagram of FIG. 2. This DDA 1 includes: a differential input stage 11 comprising NMOS transistors Q1, Q2 and Q13; a differential input stage 12 comprising NMOS transistors Q3, Q4 and Q15; an output stage 13 having a PMOS transistor Q11 and an NMOS transistor Q14; an output stage 14 having a PMOS transistor Q12 and an NMOS transistor Q16; four input terminals VPP, VPN, VNP and VNN; and two output terminals VoutP and VoutN.
Between the output terminals VoutN and VoutP, a common mode feedback circuit 15 is provided. The common mode feedback circuit 15 controls the gate voltages of PMOS transistors Q5 and Q6 which are used as common loads to the two differential input stages 11 and 12. The connection node of the transistors Q5, Q2 and Q3 controls the gate of one output stage transistor Q12, and the connection node of the transistors Q6, Q4 and Q1 controls the gate of the other output stage transistor Q11.
A resistor R11 and a capacitor C11, which are provided between the gate and drain of the output stage transistor Q11, constitute a phase compensator circuit. Similarly, a resistor R12 and a capacitor C12, which are provided between the gate and drain of the output stage transistor Q12, constitute a phase compensator circuit. The NMOS transistors Q13 through Q16 are current source transistors for controlling a bias current for each of the differential input stages 11 and 12, and are controlled by a voltage Vbias which is applied from the outside of the circuit.
The common mode feedback circuit 15 is designed to carry out a negative feedback control for suppressing a output common mode component. For example, the common mode feedback circuit 15 is formed as shown in FIG. 3. The common mode feedback circuit 15 of FIG. 3 includes: a differential input stage comprising NMOS transistors Q21, Q22 and Q23; and a load circuit comprising PMOS transistors Q24 and Q25 which are diode-connected. The gate of one transistor Q21 of the differential input stage is connected to output terminals VoutN and VoutP via resistors R21 and R22, respectively. By these resistors R21 and R22, a common mode component contained in output signals VoutN and VoutP of the balanced type DDA 1 is detected. This is compared with a reference voltage VAG applied to the gate of the other transistor Q22 and a control signal VC is generated. By this control signal VC, the negative feedback control of the DDA 1 is carried out, so that the output common mode voltage is substantially equal to the VAG.
In such a balanced type DDA 1 having four inputs and two outputs, the output signal of one output terminal VoutP has a positive gain with respect to an input signal of a difference between the input terminal VPP and the input terminal VPN, and the output signal of the other output terminal VoutN has a negative gain with respect thereto. In addition, one output terminal VoutP has a negative gain with respect to an input signal of a difference between the input terminal VNP and the input terminal VNN, and the other output terminal VoutN has a positive gain with respect thereto. These gains are determined by a product of the gain of the differential input stage by the gain of the output stage. Assuming that the mutual conductance of the MOS transistors Q1, Q2, Q3 and Q4 is gm, the drain-to-source conductance is gdsn, and the drain-to-source conductance of the MOS transistors Q5 and Q6 is gdsp, then, the gain of the differential input stage with respect to the differential input signal is gm/(gdsn+gdsp). Therefore, it can be seen that the mutual conductance of the differential transistor pair of the differential input stage is in proportion to the absolute value of the gain of the DDA 1. Using such a balanced type DDA 1, a non-inverting amplifier circuit is formed as shown in FIG. 4. This circuit comprises resistors R1 through R3 in addition to the balanced type DDA 1, and outputs VoutP and VoutN with respect to VinP and VinN. Since a negative feedback is applied to the circuit by the resistors R1 through R3, the operation of this non-linear amplifier circuit satisfies the following formula (1) assuming that the gain of the balanced type DDA 1 is infinity.
(VPPxe2x88x92VPN)xe2x88x92(VNPxe2x88x92VNN)=0xe2x80x83xe2x80x83(1)
Therefore, assuming that the resistance value of the resistor R3 is Ra and that the resistance value of the resistors R1 and R2 is Rb, the gain A of this circuit is expressed by the following formula (2).
A={Rb+(Ra/2)}/(Ra/2)xe2x80x83xe2x80x83(2)
Assuming that the common mode component of the input voltages VinP and VinN is VCMi, the differential component thereof is Vi, the common mode component of the output voltages VoutP and VoutN is VCMO, and the differential output component thereof is Vo, then, the following relationships (3) through (7) are established.
VPP=VCMi+Vixe2x80x83xe2x80x83(3)
VNP=VCMixe2x88x92Vixe2x80x83xe2x80x83(4)
VoutP=VCMO+Voxe2x80x83xe2x80x83(5)
VoutN=VCMOxe2x88x92Voxe2x80x83xe2x80x83(6)
Vo=Axc2x7Vixe2x80x83xe2x80x83(7)
Since the input terminal of the balanced type DDA 1 is connected to the gate of the MOS transistor as shown in FIG. 2, no current flows into the input terminal in principle. Therefore, VPN and VNN are determined by the resistors R1 through R3 and the output voltages VoutP and VoutN as shown in the following formulae (8) and (9).
xe2x80x83VPN=VAG+Vixe2x80x83xe2x80x83(8)
VNN=VAGxe2x88x92Vixe2x80x83xe2x80x83(9)
If VCMixe2x89xa0VCMO, then VPPxe2x89xa0VPN and VNPxe2x89xa0VNN. That is, if the common mode component VCM of the input voltage of the DDA 1 is different from the common mode component VCMO of the output voltage, two signals inputted to the differential input stage have different voltages.
Referring to FIGS. 5 and 6, the operation of the differential input stage will be considered. The differential input stage of FIG. 5 comprises NMOS transistors Q51, Q52 and Q53. The gate potential of the NMOS transistor Q53 is controlled by a voltage Vbias so as to flow a desired bias current Ibias. It is herein assumed that the gate-to-source voltage of the MOS transistor Q51 is VGS1, the drain current thereof is ID1, the gate-to-source voltage of the MOS transistor Q52 is VGS2, and the drain current thereof is ID2. Assuming that the characteristics of the MOS transistors Q51 and Q52 can be expressed by ID=K (VGSxe2x88x92VTH)2 using a gate-to-source voltage VGS, a drain current ID, a threshold voltage VTH and a mutual conductance parameter K, then, the relationship between xcex94Vi=VGS1xe2x88x92VGS2 and xcex94ID=ID1xe2x88x92ID2 is expressed by the following formula (10).
xcex94ID=xcex94Vixc2x7K{2Ibias/Kxe2x88x92(xcex94Vi)2}xc2xdxe2x80x83xe2x80x83(10)
The relationship of the formula (10) is shown in FIG. 6. It can be seen from this figure that a range (a linear operation range of a differential input stage), in which xcex94ID varies substantially linearly with respect to xcex94Vi, is inversely in proportion to K. If this range is not sufficiently large as compared with the difference between the voltages of two signals inputted to the differential input stage, distortion occurs.
Therefore, it is conventionally designed that the linear operation range of the differential input stage is sufficiently large. Assuming that the channel width of the MOS transistor is W and the channel length thereof is L, K is in proportion to W/L, so that the linear operation range of the differential input stage can be enlarged if the W/L is decreased.
However, in this method, as can be seen from FIG. 6, the mutual conductance (xcex94ID/xcex94Vi) of the differential input stage decreases, so that there is a problem in that the gain of the DDA decreases. As a result, there are other problems in that it is not possible to obtain a desired high gain, or if it is required to provide a DDA having a large gain-bandwidth product (GB product), it is required to take measures to increase the number of gain stages, and if the number of gain stages is increased, it is difficult to carry out a phase compensation.
In addition, a multiple input circuit using the balanced type DDA 1 is shown in FIG. 7. This multiple input circuit comprises the balanced type DDA 1 and resistors R1 through R7. This circuit is designed to input VinPP, VinNN, VinPn and VinNP and output VoutP and VoutN. In this circuit, in accordance with a differential component ViN between the input voltages VinPN and VinNN and a differential component ViP between the input voltages VinPP and VinNP, a differential output VoutPxe2x88x92VoutN determined by VsPxe2x88x92ViN is obtained.
In this case, since a negative feedback is applied to the circuit by the resistors R1 through R4, the operation of the circuit satisfies the above described formula (1) assuming that the gain of the balanced type DDA 1 is infinity.
Therefore, if it is set that R3=R4=Ra, R1=R2=Rb, R5=R6=Rc and R7=Rd, assuming that the differential component between the input voltages VinPN and VinNN is ViN and that the differential component between the input voltages VinPP and VinNP is ViP, the differential output component Vo of the output voltages VoutP and VoutN of this circuit is expressed by the following formula (11).                     Vo        =                                                                              (                                      Rd                    /                    2                                    )                                ⁢                                  (                                      Ra                    +                    Rb                                    )                                                                              (                                      Rc                    +                                          Rd                      /                      2                                                        )                                ⁢                Ra                                      ⁢                          xe2x80x83                        ⁢            ViP                    -                                    Rb              Ra                        ⁢                          xe2x80x83                        ⁢            ViN                                              (        11        )            
Assuming that the common mode component of the input voltages VinPN and VinNN is VCMN, the common mode component of the input voltages VinPP and VinNP is VCMP, the differential component of the output voltages VoutP and VoutN is Vo, and the common mode component thereof is VCMO, then, VPP and VPN are expressed by the following formulae (12) and (13), respectively.                     VPP        =                                                            Rd                /                2                                            Rc                +                                  Rd                  /                  2                                                      ⁢            ViP                    +          VCMP                                    (        12        )                                VPN        =                                                            (                                  Rd                  /                  2                                )                            ⁢              ViP                                      Rc              +                              Rd                /                2                                              +                                    Rb              ·              VCMN                                      Ra              +              Rb                                +                                    Ra              ·              VCMO                                      Ra              +              Rb                                                          (        13        )            
It can be seen from these formulae that VPPxe2x89xa0VPN in general. The other pair of input voltages VNP and VNN are the same. That is, in the multiple input circuit shown in FIG. 7 similar to FIG. 4, two input signals to the differential input stage have different voltages to cause distortion. In order to solve this problem, it is required to enlarge the linear operation range of the balanced type DDA 1, so that the same problem as that in FIG. 4 is caused.
As described above, there are problems in that if the conventional balanced type DDA comprises a linear amplifier circuit and a multiple input circuit, distortion occurs, that if the linear operation range is intended to be enlarged in order to reduce distortion, the gain reduces, and that if the number of gain stages is increased to compensate this, it is difficult to carry out a phase compensation.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide an amplifier circuit capable of reducing distortion without reducing gains.
It is another object of the present invention to provide a non-inverting amplifier circuit and a multiple input circuit, which use such an amplifier circuit.
According a first aspect of the present invention there is provided an amplifier circuit comprising:
a first four-input balanced amplifier having
a first differential terminal pair and a second differential terminal pair;
a first output terminal and a second output terminal, output signals at the first output terminal and the second output terminal being complementary; and
a second four input single-ended amplifier having
a third differential terminal pair and a fourth differential terminal pair;
a third output terminal;
wherein the first differential terminal pair and the third differential terminal pair are connected in parallel, and the second differential terminal pair and the fourth differential terminal pair are connected in reverse parallel.
According a second aspect of the present invention there is provided an amplifier circuit comprising:
a first four-input balanced amplifier having
a first differential terminal pair and a second differential terminal pair;
a first output terminal and a second output terminal, output signals at the first output terminal and the second output terminal being complementary; and
a second four input single-ended amplifier having
a third differential terminal pair and a fourth differential terminal pair;
a third output terminal;
wherein the first differential terminal pair and the third differential terminal pair are connected in reverse parallel, and the second differential terminal pair and the fourth differential terminal pair are connected in parallel.
According to the present invention, a balanced type DDA, to which input terminals are commonly connected, is combined with a single end type DDA, so that the output terminal of the single end type DDA serves as a control output terminal. By carrying out a negative feedback control on the basis of the output of the control output terminal, a virtual short-circuit can be established between first and second input terminals and between third and fourth input terminals. Therefore, it is possible to reduce distortion without reducing gains.